1. Field of the Invention
The present invention generally relates to semiconductor devices and more particularly to a method for doping fin-based semiconductor devices by using ion implantation.
2. Description of the Related Technology
Scaling down of silicon MOS devices has become a major challenge in the semiconductor industry. Whereas at the beginning, device geometrical shrinking already gave a lot of improvements in IC performance, nowadays new techniques, methods, materials and device architectures have to be introduced beyond the 90 nm technology node.
One major problem when scaling conventional planar devices are the short channel effects which start to dominate over the device performance. A solution for this problem came with the introduction of the multi-gate field effect transistor (MUGFET), also often referred to as fin-based semiconductor device or FINFET. Due to their three dimensional architecture, with the gate wrapped around a thin semiconductor fin, an improved gate control (and thus less short channel effects) over the channel could be achieved by using multiple gates.
An important issue for the fabrication of these MUGFETs is the uniform doping of the source-drain extensions. For conventional planar devices source-drain extensions can easily be performed by doing ion implantation. In this way source-drain regions can be made in the plane of the wafer surface. For MUGFETs however the doping of the source-drain extensions has to be done in a three dimensional way. More particularly doping of the top surface and doping of the sidewall surfaces of the fin is necessary. This is typically done by applying two ion implantation steps, as also described in U.S. Patent application US2004/0217433. In a first step dopant ions are implanted at a tilt angle α with respect to the normal of the top surface of the semiconductor fin in order to dope the left (first) sidewall surface and the top surface. In a second step dopant ions are implanted at a tilt angle −α with respect to the normal of the top surface of the semiconductor fin in order to dope the right (second) sidewall surface and the top surface. Due to the use of a focus beam with a good control of the tilt angle α of the incoming ion, the distribution of the implanted dose at the top of the fin versus the implanted dose at the sidewalls of the fin is always non-uniform. In addition the equivalent energy is different on the top and on the side of the fin since a tilt angle different from 45 degrees is used. More particularly, with the method as described in U.S. Patent application US2004/0217433 the top surface of the fin will receive twice the dose compared to the dose received at the sidewalls of the fin. More specifically, the sheet resistance ratio, which is the sheet resistance at the top surface versus the sheet resistance at the sidewall surfaces, is 2:1. This results in source-drain extension junctions which are not uniform (or conformal) all along the fin. This is not optimal for the device performance and short channel effect control. To have uniform doping a sheet resistance ratio close to 1 is required.
Furthermore for 32 nm high density circuits, these extension implantations are limited to an angle smaller than 10 degrees, which makes it again more difficult to get a uniform doping profile all along the fin.
It is thus desirable to provide a method for doping a multi-gate device that overcomes the drawbacks as described above. More specifically it is desirable to provide a method for doping a multi-gate device such that the sheet resistance ratio at the top surface to the sidewall surfaces is close to 1.